Blocking the clock signal

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Let's say I need to find out that the BLOCK signal came earlier than the 5 clk signal. These signals are asynchronous to each other, so I can't use the classic construction as shown below.

always(posedge clk)
if(cnt==4 && !BLOCK)
flag<=1;
else 
flag<=0;
//The flag will be set to 1 only if the BLOCK signal does not arrive before 5 clk.

always(posedge clk)
cnt <= cnt + 1;

But I can block clk when the BLOCK signal arrives so that it stops clocking flag and the flag is not set to 1.

wire clk_flag = clk & !BLOCK;

always(posedge clk_flag)
if(cnt==4)
flag<=1;
else 
flag<=0;

//The flag will be set to 1 only if the BLOCK signal does not arrive before 5 clk

always(posedge clk)
cnt <= cnt + 1;

Is it acceptable to mix signals through "and" for clk in design?

I have not seen such solutions, but I do not see anything dangerous for the design here, I do not know how to solve the problem with signals in another way. Or maybe someone knows how to solve the problem of determining which of the two signals came earlier (the fifth clk or BLOCK) if they are asynchronous? Thanks.



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